PROCESSEUR PA-RISC 7300LC SOCKET 463 1996 EN FRANCE

The PA-7300LC The First "System on a Chip" Presented at Microprocessor Forum on 10/16/95 by Tom Meyer The PA-7300LC is a new processor design, which features a high level of integration of system functions. HP's PA-RISC processor family currently features two "streams" of CPU development. Each is optimized to meet the needs of different classes of computer systems. The high-end stream, which includes the PA-7200 and PA-8000 chips, is optimized for very high performance, highly expandable power desktops and servers. Several years ago it was determined that HP could best meet the needs of higher volume, more cost sensitive products by developing a different set of CPUs tuned to the special requirements of these systems. This processor line began with the PA-7100LC, which first began shipping in January of 1994, and continues with the new design described in this paper. We refer to this as our "low end" but it is also a "no compromise" stream, since we consider cost, performance, power, and other design objectives to all be equally high priority. Meeting the design objectives by finding the right balance between these factors is the main challenge in this area of microprocessor design. Design Objectives The design objectives of the PA-7300LC chip are nearly identical to those of its predecessor, which has proven to be a successful volume work-horse processor. Design improvements and a more advanced VLSI technology have allowed the designers to achieve roughly twice the performance of the 100MHz PA-7100LC without compromising cost or any of the other objectives. Like previous PA-RISC chips, the team evaluated the cost of design tradeoffs using a holistic approach which emphasizes total system cost, rather than just trying to design a cheap microprocessor without regard to the rest of the system. In defining the PA-7300LC HP's design team carefully considered the requirements of realistic system applications and tuned the design to meet those needs rather than just optimizing for microprocessor-level benchmarks. As a result, a large part of the design effort focused on minimizing the number of system components, reducing test and diagnostic costs, and getting the right level of functional partitioning. System designers and manufacturing engineers were consulted throughout the design. As you will see, many chip level features have been included to address these objectives. PA-7300LC Overview This design features a superscalar processor core that was highly leveraged from the PA-7100LC core. Enhancements include a large on-chip primary cache, an integrated DRAM and L2 cache controller, and an improved I/O bus controller. The chip uses established technologies including HP's half micron CMOS process and a low-cost ceramic pin-grid array package. The preliminary performance projections you see here assume 1 Mbyte of secondary cache and 60ns fast-page-mode DRAMs, but the chip can be configured with higher performance memory components. We believe that this processor will do very well on memory intensive programs as shown by the SPEC95 and OLTP estimates. This is because of the highly optimized memory hierarchy I will describe in a moment. PA-7300LC Chip Layout The RISC processor core, consisting of the integer units, floating-point unit, and instruction decode logic occupy the right side of the die. The center blocks contain the virtual memory translation lookaside buffer (TLB) and Memory and I/O controller or MIOC. The large, denser-looking blocks are the instruction and data caches. Nearly 8 million of the 9.2 million transistors are contained in these two blocks. As you can see, a large amount of chip real estate is devoted to embedded SRAM for the primary caches. It's been said that future microprocessors will look like large memory chips with a small microprocessor block in the corner. The 7300LC has really headed in that direction with this chip since the cache arrays occupy 40% of the chip area. As a si